In a process of manufacturing, for example, a semiconductor device, an etching processing such as, for example, plasma etching, has conventionally been performed on a substrate such as, for example, a semiconductor wafer to form, for example, a fine circuit pattern. In such an etching process, formation of a mask has been performed through a photolithography process using a photoresist.
In the photolithography process, in order to cope with miniaturization of the formed pattern, various technologies have been developed. As one of them, there is so-called double patterning. In the double patterning, patterning is performed in two stages which includes a first patterning step for forming a first pattern, and a second patterning step for forming a second pattern after the first patterning step so as to form a mask with a more fine interval than a mask formed by single patterning (see, e.g., Patent Document 1).
As such a double patterning technology, a so called side wall transfer technology is known in which a layer containing silicon such as, for example, amorphous silicon, is patterned into a predetermined pattern (e.g., a line and space pattern), a film such as, for example, a silicon oxide layer or a silicon nitride layer, is formed on the side wall portion of the pattern of the silicon-containing layer, and then, the pattern of the silicon-containing layer surrounded by the film is removed through etching so that the silicon oxide layer or the silicon nitride film layer formed on the side wall portion of the pattern of the silicon is left. In such a double patterning technology, the silicon-containing layer surrounded by, for example, the silicon oxide layer or the silicon nitride layer, has conventionally been removed by plasma etching using a gas system such as, for example, HBr or Cl2.